`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:22:09 10/06/2011
// Design Name:   RAM
// Module Name:   C:/Users/Chase/16bitcpu/RamBlcokTEst.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RAM
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RamBlcokTEst;

	// integer
	integer i = 0;
		
	// Inputs
	reg [15:0] DI;
	wire [1:0] DOP;
	reg [9:0] ADDR;
	reg CLK;
	reg RESET;
	reg WE;
	reg EN;

	// Outputs
	wire [15:0] DO;

	// Instantiate the Unit Under Test (UUT)
	RAM uut (
		.DI(DI), 
		.DO(DO), 
		.ADDR(ADDR), 
		.CLK(CLK), 
		.RESET(RESET), 
		.WE(WE), 
		.EN(EN)
	);

	initial begin
		// Initialize Inputs
		DI = 0;
		ADDR = 0;
		CLK = 0;
		RESET = 0;
		WE = 0;
		EN = 1;
		$monitor("DO: %d, ADDR: %d, DI: %d", DO, ADDR, DI);// Display to user READING DATA and WRITING DATA

		// Wait 100 ns for global reset to finish
		#100;
		
		// Add stimulus here
		RESET=1;
		#30
		RESET=0;

		#20
		
//--------------Code Starts Here------------------ 
  // Memory Write Block 
  // Write Operation : When WE = 1
  WE = 1;
  
		for ( i= 0; i < 100; i = i + 1)
		begin
			DI = i;
			ADDR = i;
			#20; // WAIT 30
		end
		
//--------------Code Starts Here------------------ 
  // Memory  Block 
  // Write Operation : When WE = 0
  	#20; // WAIT 30
  WE = 0;
  
		for ( i= 0; i < 100; i = i + 1)
		begin
		// check if data out is equal to what was written to the same address
			ADDR = i;
			if (DO == i)
				$display("Data found at address: %d , Data: %d", ADDR, DO); // Display to user READING DATA
			#20; // WAIT 30
		end
		
		
 end
		always begin
		#10 CLK=~CLK;
		end
		
endmodule

